The present invention relates to a method for clock synchronization in the transmission of digital information signals on two-wire transmission lines between a superordinate system, in particular a PCM time multiplex exchange, and a subordinate system, in particular a digital subscriber station. The digital information signals take the form of message signal blocks comprising at least one message signal word and a prefixed synchronization word. The clock generators which determine the time relationship of the superordinate and subordinate systems operate plesiochronously (close in time) to each other. In this mode the subordinate system periodically repeats an odd number of directly succeeding time periods or intervals which are derived from the bit cycle of the clock signal produced by the subordinate system clock generator. The one time interval located in the middle of this succession of time periods coincides with an edge of the bit clock pulse sequence. A "receive pulse" is then derived from the pulse edge of one of the bits of the message signal blocks received from the superordinate system, and a phase comparison is made to determine whether this receive pulse falls into one of the mentioned time intervals.
In above described transmission of digital message signals in the form of message signal blocks, it is necessary, first of all, to receive these blocks correctly in time. In order to effect this synchronization a synchronization word is sent to the subordinate system with each message signal block. Provision must be made, in this connection, to prevent a simulation of the synchronization word, either by message signal bit combinations occurring over a protracted period of time or disturbances occurring during the receiving time periods of the respective systems, from leading to a mis-synchronization.
In addition to the message block synchronization, however, it is also necessary to effect a clock synchronization. In the above noted mode of operation problems may arise because the clock information must be derived in the subordinate system from the incoming digital information signals. A separate transmission of the clock is not provided. If the message signal blocks for the two transmission directions are transmitted alternately, such a clock may be derived in the subordinate system only during a part of the transmit/receive period (namely, during the receive period) and therefore the remaining part of transmit/receive period (the transmit period) as well as the pause interval must be bridged by the synchronization circuit.
There are two situations in which the digital information signals received at a subordinate system will be out of phase with the locally generated clock signal: phase deviations caused by imprecise synchronization of the clock generators in the superordinate and subordinate systems, and also brief phase fluctuations caused by disturbances in transmission. Unlike the first-mentioned phase deviations, the phase fluctuations are not cumulative; consequently, they should be disregarded in the clock synchronization, if they do not exceed a certain magnitude, and should not lead to a readjustment of the phase relationships.
It has therefore been proposed, as indicated above, to derive a succession of time periods or intervals in the subordinate system from the bit clock fixed by the clock generator, and to derive a "receive pulse" from the bits of the message signal blocks received from the superordinate system. A phase comparison is then undertaken to determine whether the receive pulse falls into one of these time periods. According to the proposed method, all bits of one binary value of the message signal blocks are utilized in the derivation of the receive pulse. If only small phase fluctuations are involved, the decision whether or not to make a phase correction is made dependent upon the number of deviations found within a given transmit/receive period. In this way the precision of the synchronization method depends upon the number of bits of the one value ("0" or "1") from which the receive pulses are derived. Especially when the message signal blocks do not contain stochastic information, but serve to transmit slowly changing data, they may lead to inaccuracies in synchronization.
It is, therefore, an object of the present invention to provide a clock synchronization method which is independent of the message content of the information blocks. It is a further object of the present invention to provide a synchronization method which may be adapted, with minimal expense, to all cases of operation which lie between the one extreme case wherein the frequency deviations between the clock generators of the superordinate and subordinate systems are relatively great while the instantaneous phase fluctuations are small, and the other case wherein, although the clock generators have a high frequency constance, the phase fluctuations independent of their mode of operation are considerable.